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PI6C102
Precision Clock Synthesizer for Mobile PCs
Features
Two copies of CPU clock with VDD of 2.5V 5% 100 MHz or 66.6 MHz operation Six copies of PCI clock, (synchronous with CPU clock) 3.3V One copy of Ref. Clock @ 14.31818 MHz (3.3VTTL) Low cost 14.31818 MHz crystal oscillator input Power management control Isolated core VDD, VSS pins for noise reduction 28-pin SSOP package (H)
Description
The PI6C102 is a high-speed low-noise clock generator designed to work with the Pericom's PI6C18x clock buffer to meet all clock needs for Mobile Intel Architecture platforms. CPU and chipset clock frequencies of 66.6 MHz and 100 MHz are supported. Split supplies of 3.3V and 2.5V are used. The 3.3V power supply powers a portion of the I/O and the core. The 2.5V is used to power the remaining outputs. 2.5V signaling follows JEDEC standard 8-X. Power sequencing of the 3.3V and 2.5V supplies is not required. An asynchronous PWRDWN# signal may be used to orderly power down (or up) the system.
Block Diagram
Pin Configuration
XTAL_IN XTAL_OUT
REF VDDCPU
*KBBAHI
XTAL_IN XTAL_OUT PWRDWN# SEL SEL100/66# 2 CPUCLK [0:1] VDDREF REF OSC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28-Pin H
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VSSREF VDDREF REF VDDCPU CPUCLK0 CPUCLK1 VSSCPU VDDCORE1 VSSCORE1 PCISTOP# CPUSTOP# PWRDWN# SEL SEL100/66#
VSSPCI0 PCICLK_F PCICLK1 VDDPCI0 PCICLK2 PCICLK3 VDDPCI1 PCICLK4 PCICLK5 VSSPCI1 VDDCORE0 VSSCORE0
PLL1 DIV
CPUSTOP# VDDCPU0,1 PCISTOP# 5
PCICLK [1:5] PCICLK_F
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PI6C102 Precision Clock Synthesizer for Mobile PCs
Pin Description
Pin 1 2 3,12 4 5,7,8,10,11 6,9 21 20 15 16 17 18 19 22 23,24 25 26 27 28 Signal Name XTAL_IN XTAL_OUT VSSPCI[0:1] PCICLK_F PCICLK[1:5] VDDPCI [0:1] VDDCORE 1 VSSCORE 1 SEL100/66# SEL PWRDWN# CPUSTOP# PCISTOP# VSSCPU CPUCLK[0:1] VDDCPU REF VDDREF VSSREF Type I O ground O O power power ground I I I I I ground O power O power ground Qty. 1 1 2 1 5 2 1 1 1 1 1 1 1 1 2 1 1 1 1 14.318 MHz crystal input 14.318 MHz crystal output Ground for PCI clock outputs Free running PCI clock output PCI clock outputs, TTL comatible 3.3V Power for PCI clock outputs Isolated power for core Isolated ground for core Select pin for enabling 100 MHz or 66 MHz H = 100 MHz. L = 66 MHz Test or Active Mode Select Powers down device when held LOW Stops CPU clocks LOW if held LOW Stops PCI clocks LOW if held LOW Ground for CPU outputs CPU and Host clock outputs 2.5V Power for CPU outputs 14.318 MHz clock output Power for REF outputs Ground for REF outputs De s cription
Select Functions
SEL100/66# 0 0 1 1 SEL 0 1 0 1 Function Hi- Z 66 MHz active Test Mode 100 MHz active
Function De s cription Hi- Z Test Mode
Outputs CPU [0:1] Hi- Z TCLK/2 PCI[0:5], PCIF Hi- Z TCLK/6 REF Hi- Z TCLK
Clock Enable Configuration
CPU_STOP# X 0 0 1 1 PCI_STOP# X 0 1 0 1 PWR_D WN# 0 1 1 1 1
Notes: TCLK is a test clock over driven on he XTAL_IN inpu during test mode.
CPUCLK [0:1] PCICLK[1:5] PCICLK_F low low low 100/66 MHz 100/66 MHz low low 33 MHz low 33 MHz low 33 MHz 33 MHz 33 MHz 33 MHz Othe r Clocks stopped running running running running Crys tal off running running running running VCO's off running running running running
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PI6C102 Precision Clock Synthesizer for Mobile PCs
Power Management Timing
Signal CPU_STOP# Signal State 0 (disabled) 1 (enabled) PCI_STOP# 0 (disabled) 1 (enabled) PWR_DWN# 1 (normal operation) 0 (power down) Late ncy No. of ris ing e dge s of fre e running PCICLK 1 1 1 1 3ms 2 max.
Notes: 1. Clock on/off latency is defined as the number of rising edges of free running PCICLKs between when the clock disable goes low/high to when the first valid clock comes out of the device. 2. Power-up latency is from when PWR_DWN# goes inactive (HIGH) to when the first valid clocks are driven from the device.
CPUCLK (Internal) CPUCLK (Internal) PCICLK_F (Free-running) CPU_STOP# PCI_STOP# PWR_DWN# CPUCLK (External)
CPU_STOP# Timing Diagram Notes: 1. All timing is referenced to the CPUCLK. 2. The Internal label means inside the chip and is a reference only. 3 CPU_STOP# is an input signal that must be made synchronous to the free running PCI_F. 4. ON/OFF latency shown in the diagram is 2 CPU clocks. 5. All other clocks continue to run undisturbed. 6. PWR_DWN# and PCI_STOP# are shown in a HIGH state. 7. Diagrams shown with respect to 66 MHz. Similar operation as CPU = 100 MHz. CPU_STOP# is an input signal used to turn off the CPU clocks for low power operation. CPU_STOP# is asserted asynchronously by the external clock control logic with the rising edge of free running PCI clock and is internally synchronized to the external PCICLK_F output. All other clocks continue to run while the CPU clocks are
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disabled. The CPU clocks are always stopped in a LOW state and started guaranteeing that the high pulse width is a full pulse. CPU clock on latency is 2 or 3 CPU clocks and CPU clock off latency is 2 or 3 CPU clocks.
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PI6C102 Precision Clock Synthesizer for Mobile PCs
PCI_STOP# is an input signal used to turn off PCI clocks for low power operation. PCI clocks are stopped in the LOW state and
started with a guaranteed full high pulse width. There is ONLY one rising edge of external PCICLK after the clock control logic.
CPUCLK (Internal) PCICLK (Internal) PCICLK_F (Free-running) CPU_STOP# PCI_STOP# PWR_DWN# PCICLK (External)
PCI_STOP# Timing Diagram Notes: 1. All timing is referenced to the CPUCLK. 2. PCI_STOP# signal is an input signal which must be made synchronous to PCI_F output. 3 Internal means inside the chip. 4. All other clocks continue to run undisturbed. 5. PWR_DWN# and CPU_STOP# are shown in a high state. 6. Diagrams shown with respect to 66 MHz. Similar operation as CPU = 100 MHz. The PWR_DWN# is used to place the device in a very low power state. PWR_DWN# is an asynchronous active low input. Internal clocks are stopped after the device is put in power-down mode. The power-on latency is less than 3ms. PCI_STOP# and CPU_STOP# are dont cares during the power-down operations. The REF clock is stopped in the LOW state as soon as possible.
CPUCLK (Internal) PCICLK (Internal) PWR_DWN# CPUCLK (External) PCICLK (External) VCO Crystal
PWR_DWN# Timing Diagram Notes: 1. All timing is referenced to the CPUCLK. 2. The Internal label means inside the chip and is a reference only. 3. PWR_DWN# is an asynchronous input and metastable conditions could exist. The signal is synchronized inside the part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown wth respect to 66 MHz. Similar operation as CPU = 100 MHz.
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PI6C102 Precision Clock Synthesizer for Mobile PCs
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ............................................................... 65C to +150C Ambient Temperature with Power Applied ................................ 0C to +70C 3.3V Supply Voltage to Ground Potential ................................... 0.5V to +4.6V 2.5V Supply Voltage to Ground Potential ................................... 0.5V to +3.6V DC Input Voltage ....................................................................... 0.5V to +4.6V Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC Electrical Characteristics (VDDQ3 = +3.3V 5%, VDDQ2 = +2.5V 5%, TA = 0C to +70C)
PI6C102 Condition Powerdown Mode (PWRDWN# =0) Active 66 MHz SEL 100/66# = 0 Active 100 MHz SEL 100/66# = 1 M ax. 2.5V Supply Cons umption M ax. dis cre te cap loads , VDDQ2 = 2.625V All s tatic inputs = VDDQ3 or VSS 100A 72mA 100mA M ax. 3.3V Supply Cons umption M ax. dis cre te cap loads , VDDQ3 = 3.465V All s tatic inputs = VDDQ3 or VSS 500A 170mA 170mA
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PI6C102 Precision Clock Synthesizer for Mobile PCs
DC Operating Specifications
Symbol VDD = 3.3V 5% VIH3 VIL3 IIL VDD = 2.5V 5% VOH2 VOL2 VDD = 3.3V 5% VOH3 VOL3 VDD = 3.3V 5% VPOH VPOL PCI Bus output high voltage PCI Bus output low voltage IOH = - 1mA IOL = 1mA 2.4 0.55 V Output high voltage Output low voltage IOH = - 1mA IOL = 1mA 2.4 0.4 V Output high voltage Output low voltage IOH = - 1mA IOL = 1mA 2.0 0.4 V Input high voltage Input low voltage Input leakage current 0 < VIN < VDD VDD 2.0 VSS - 0.3 -5 VDD +0.3 0.8 +5 V A Parame te rs Conditions M in. M ax. Units
CIN CXTAL COUT LPIN TA
Input pin capacitance Xtal pins capacitance Output pin capacitance Pin Inductance Ambient Temperature No airflow 0 13.5 18.0
5 22.5 6 7 70 nH C pF
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PI6C102 Precision Clock Synthesizer for Mobile PCs
Buffer Specifications
Buffe r Name CPU REF PCI VDD Range (V) 2.375 - 2.625 3.135 - 3.465 3.135 - 3.465 Impe dance () 13.5 - 45 20 - 60 12 - 55 Buffe r Type Type 1 Type 3 Type 5
Type 1: CPU Clock Buffers (2.5V)
Symbol IOHMIN IOHMAX IOLMIN IOLMAX tRH tFH Parame te rs Pull- up current Pull- up current Pull- down current Pull- down current 2.5V Type 1 output rise edge rate 2.5V Type 1 output fall edge rate Conditions VOUT = 1.0V VOUT = 2.375V VOUT = 1.2V VOUT = 0.3V 2.5V 5% @ 0.4V- 2.0V 2.5V 5% @ 2.0V- 0.4V 1 1 27 30 4 4 V/ns M in. - 27 - 27 mA Typ. M ax. Units
Type 3: REF (3.3V)
Symbol IOHMIN IOHMAX IOLMIN IOLMAX tRH tFH Parame te rs Pull- up current Pull- up current Pull- down current Pull- down current 3.3V Type 3 output rise edge rate 3.3V Type 3 output fall edge rate Conditions VOUT = 1.0V VOUT = 2.375V VOUT = 1.2V VOUT = 0.3V 3.3V 5% @ 0.4V- 2.4V 3.3V 5% @ 2.4V- 0.4V 0.5 0.5 29 27 2 2 V/ns M in. - 29 - 23 mA Typ. M ax. Units
Type 5: PCI Clock Buffers (3.3V)
Symbol IOHMIN IOHMAX IOLMIN IOLMAX tRH tFH Parame te rs Pull- up current Pull- up current Pull- down current Pull- down current 3.3V Type 5 output rise edge rate 3.3V Type 5 output fall edge rate Conditions VOUT = 1.0V VOUT = 3.135V VOUT = 1.95V VOUT = 0.4V 3.3V 5% @ 0.4V- 2.4V 3.3V 5% @ 2.4V- 0.4V 1 1 30 38 4 4 V/ns M in. - 33 - 33 mA Typ. M ax. Units
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PI6C102 Precision Clock Synthesizer for Mobile PCs
AC Timing
Figure 1. Hos t Clock to PCI CLK Offs e t tHKP (2.5V) tHKH (2.5V) tHKL (2.5V) tHRISE (2.5V) tHFALL (2.5V) tJITTER (2.5V) Duty Cycle (2.5V) tHSKW (2.5V) tPZL, tPZH tPLZ, tPHZ tHSTB tPKP tPKPS
tPKH
Parame te rs Host CLK period Host CLK high time Host CLK low time Host CLK rise time Host CLK fall time Host CLK Jitter Measured at 1.25V Host Bus CLK Skew Output enable delay Output disable delay Host CLK Stabilization from power- up PCI CLK period PCI CLK period stability PCI CLK high time PCI CLK low time PCI Bus CLK Skew Host to PCI Clock Offset PCI CLK Stabilization from power- up
66 M Hz M in. 15.0 5.2 5.0 0.4 0.4 1.6 1.6 250 45 55 175 1.0 1.0 8.0 8.0 3 30.0 500 12.0 12.0 500 1.5 4.0 3 M ax. 15.5
100 M Hz M in. 10.0 3.0 2.8 0.4 0.4 1.6 1.6 250 45 55 175 1.0 1.0 8.0 8.0 3 30.0 500 12.0 12.0 500 1.5 4.0 3 M ax. 10.5
Units
ns
ps % ps ns ms ns ps ns ps ns ms
tPKL tPSKW tHPOFFSET tPSTB
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Interface
Interface
Clocking
Clocking 1.25
Host CLK
Host CLK
PCI CLK
PCI CLK
(TTL)
t HPOFFSET
3.3V
2.5V
0.4
1.5
2.4
0.4
2.0
Figure 1. Host Clock and PCI CLK Timing
Figure 2. Clock Output Waveforms
tHrise tPrise
1.25V 1.25V
Output Buffer
t HSKW
1.5V
tHKH
tPKH
1.5V
t PSKW
Duty Cycle
9
Test Load tHKP tPKP tHfall tPfall Test Point
1.25V
tPKL
tHKL
PI6C102 Precision Clock Synthesizer for Mobile PCs
1.25V
1.5V
t HPOFFSET
2.5V
3.3V
V
V
V
2.5V
3.3V
V
SS
SS
SS
SS
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PI6C102 Precision Clock Synthesizer for Mobile PCs
PCB Layout Suggestion
FB1
1 2
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VSS VDD
C7 FB2 C6 VCC
VCC C1 C2 22uF
VSS
3 4 5
VDD
C8
VDD
6 7
VSS VDD VSS
22uF C5
C3 VDD
8 9 10 11
C4
VSS VDD VSS
12 13 14
Via to VDD Plane Via to GND Plane Void in Power Plane
Note: This is only a suggested layout. There may be alternate solutions depending on actual PCB design and layout. As a general rule, C2-C7 should be placed as close as possible to their respective VDD.
Recommended capacitor values: C2-C7 ............... 0.1F, ceramic C1, C8 ............. 22F
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PI6C102 Precision Clock Synthesizer for Mobile PCs
Minimum and Maximum Expected Capacitive Loads
Clock CPU Clocks (HCLK ) PCI Clocks (PCLK ) REF M in. Load 10 30 10 M ax. Load 20 30 20 pF Units Note s 1 device load, possible 2 loads Meets PCI 2.1 requirements 1 device load
Notes: 1. Maximum rise/fall times are guaranteed at maximum specified load for each type of output buffer. 2. Minimum rise/fall times are guaranteed at minimum specified load for each type of output buffer. 3. Rise/fall times are specified with pure capacitive load as shown. Testing is done with an additional 500 resistor in parallel.
Design Guidelines to Reduce EMI
1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value for CI is 10pF. Series resistor value can be increased to reduce EMI provided that the rise and fall time are still within the specified values. 2. Minimize the number of vias of the clock traces. 3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing clock traces from plane to plane (refer to rule #2). 4. Position clock signals away from signals that go to any cables or any external connectors.
21$+
2 CPUCLK CL 6 PCICLK CL 22/33 REF CL 1 Device load 33 Meets PCI2.1 Req. 32 1 Device load
Ordering Information
P/N PI6C102H D e s cription 28- pin SSO P Package
Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com
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